1 data sheet acquired from harris semiconductor schs139 features ? hysteresis on clock inputs for improved noise immu- nity and increased input rise and fall times ? asynchronous reset ? complementary outputs ? buffered inputs ? typical f max = 60mhz at v cc = 5v, c l = 15pf, t a = 25 o c ? fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads ? wide operating temperature range . . . -55 o c to 125 o c ? balanced propagation delay and transition times ? signi?cant power reduction compared to lsttl logic ics ? hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v ? hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 m a at v ol , v oh description the harris cd74hc107 and cd74hct107 utilize silicon gate cmos technology to achieve operating speeds equivalent to lsttl parts. they exhibit the low power consumption of standard cmos integrated circuits, together with the ability to drive 10 lsttl loads. these ?ip-?ops have independent j, k, reset and clock inputs and q and q outputs. they change state on the negative-going transition of the clock pulse. reset is accomplished asynchronously by a low level input. this device is functionally identical to the hc/hct73 but differs in terminal assignment and in some parametric limits. the 74hct logic family is functionally as well as pin compatible with the standard 74ls family. pinout cd74hc107, cd74hct107 (pdip, soic) top view ordering information part number temp. range ( o c) package pkg. no. cd74hc107e -55 to 125 14 ld pdip e14.3 cd74hct107e -55 to 125 14 ld pdip e14.3 CD74HC107M -55 to 125 14 ld soic m14.15 notes: 1. when ordering, use the entire part number. add the suf?x 96 to obtain the variant in the tape and reel. 2. wafer and die is available which meets all electrical specifications. please contact your local sales office or harris customer service for ordering information. 1j 1q 1q 1k 2q 2q gnd v cc 1r 1cp 2k 2r 2cp 2j 1 2 3 4 5 6 7 14 13 12 11 10 9 8 march 1998 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1998 file number 1722.1 cd74hc107, cd74hct107 dual j-k flip-flop with reset negative-edge trigger [ /title (cd74 hc107 , cd74 hct10 7) / sub- j ect (dual j-k flip- flop with reset nega- tive-
2 functional diagram logic diagram truth table inputs outputs r cp j k q q lxxxlh h l l no change h hlhl h lhlh h h h toggle h h x x no change note: h = high level (steady state) l = low level (steady state) x = irrelevant = high-to-low transition 2 r 3 2 1 q 1q 10 13 1 r 2k 11 9 5 6 2 q 2q 2 cp ff 1 ff 2 gnd = 7 v cc = 14 2j 8 1k 4 12 1 cp 1j 1 na j k cl cl r 3 (5) q 2 (6) q 1 (8) 4(11) j k 12 (9) cp 13 (10) r cd74hc107, cd74hct107
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 maximum junction temperature (hermetic package or die) . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 3. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads ---------v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads ---------v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 m a cd74hc107, cd74hct107
4 quiescent device current i cc v cc or gnd 0 6 - - 4 - 40 - 80 m a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos load v oh v ih or v il - 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -0.02 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il -4 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 0.02 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 4 5.5 - 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 5.5 - - 4 - 40 - 80 m a additional quiescent device current per input pin: 1 unit load d i cc (note 4) v cc - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m a note: 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads all 0.3 note: unit load is d i cc limit speci?ed in dc electrical speci?ca- tions table, e.g., 360 m a max at 25 o c. prerequisite for switching speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types cp pulse width t w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns r pulse width t w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns cd74hc107, cd74hct107
5 setup time, j, k to cp t su - 2 100 - - 125 - 150 - ns 4.5 20 - - 25 - 30 - ns 6 17 - - 21 - 26 - ns hold time, j, k to cp t h -23--3-3-ns 4.5 3 - - 3 - 3 - ns 63--3-3-ns removal time t rem - 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns cp frequency f max - 2 6 - - 5 - 4 - mhz 4.5 30 - - 25 - 20 - mhz 6 35 - - 29 - 23 - mhz hct types cp pulse width t w - 4.5 18 - - 23 - 27 - ns r pulse width t w - 4.5 24 - - 30 - 36 - ns setup time, j, k to cp t su - 4.5 20 - - 25 - 30 - ns hold time, j, k to cp t h - 4.5 5 - - 5 - 5 - ns removal time t rem - 4.5 12 - - 15 - 18 - ns cp frequency f max - 4.5 28 - - 22 - 19 - mhz switching speci?cations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay, cp to q t plh , t phl c l = 50pf 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns c l = 15pf 5 - 14 - ----ns c l = 50pf 6 - - 29 - 37 - 43 ns propagation delay, cp to q t plh , t phl c l = 50pf 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns c l = 15pf 5 - 14 - ----ns c l = 50pf 6 - - 29 - 37 - 43 ns propagation delay, r to q, q t plh , t phl c l = 50pf 2 - - 155 - 195 - 235 ns 4.5 - - 31 - 39 - 47 ns c l = 15pf 5 - 13 - ----ns c l = 50pf 6 - - 26 - 33 - 40 ns output transition time t tlh , t thl c l = 50pf 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns input capacitance c i - - - - 10 - 10 - 10 pf cp frequency f max c l = 15pf 5 - 60 - ----mhz prerequisite for switching speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max cd74hc107, cd74hct107
6 power dissipation capacitance (notes 5, 6) c pd - 5-31-----pf hct types propagation delay, cp to q t plh , t phl c l = 50pf 4.5 - - 43 - 54 - 65 ns c l = 15pf 5 - 18 - ----ns propagation delay, cp to q t plh , t phl cl = 50pf 4.5 - - 40 - 50 - 60 ns c l = 15pf 5 - 17 - ----ns propagation delay, r to q, q t plh , t phl cl = 50pf 4.5 - - 38 - 48 - 57 ns c l = 15pf 5 - 16 - ----ns output transition time t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i - - - - 10 - 10 - 10 pf cp frequency f max c l = 15pf 5 - 56 - ----mhz power dissipation capacitance (notes 5, 6) c pd - 5-30-----pf notes: 5. c pd is used to determine the dynamic power consumption, per flip-flop. 6. p d =c pd v cc 2 f i + s c l v cc 2 f o where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?cations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hct clock pulse rise and fall times and pulse width figure 3. hc and hcu transition times and propaga- tion delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = f cl i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd74hc107, cd74hct107
7 figure 5. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 6. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits test circuits and waveforms (continued) t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd74hc107, cd74hct107
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated
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